The invention relates to a memory cell configuration which is suitable, inter alia, as a read-only memory. Memory configurations to which data are permanently written in digital form are referred to as read-only memories, or ROMs.
Plastic disks, so-called compact disks or CDs, coated with aluminum are in widespread use as read-only memories for very large volumes of data. These plastic disks have two different kinds of point-like depressions in the coating, which are assigned to the logic values zero and one. The information is stored digitally in the arrangement of the depressions.
In order to read the data which are stored on a compact disk, the point-like depressions are scanned by means of a laser diode and a photocell. This requires a reader equipped with moving parts that are subjected to mechanical wear, require a comparatively large volume and allow only slow data access. The reading apparatus is furthermore sensitive to vibrations and can thus be used only to a limited extent in mobile systems.
Semiconductor-based storage devices are also known. See, for example, commonly assigned U.S. Pat. No. 5,973,373 (German patent DE 44 34 725 C1). These semiconductor-based memories have MOS transistors as memory cells. The transistors are selected via the gate electrode connected to a word line. The input of the MOS transistor is connected to a reference line, and the output is connected to a bit line. An assessment is carried out during the reading operation to determine whether or not a current is flowing through the transistor. The logic values zero and one are assigned accordingly. In technical terms, the storage of zero and one is effected as follows: in memory cells in which the logic value assigned to the state xe2x80x9cno current flow through the transistorxe2x80x9d is stored, no MOS transistor is fabricated or no conductive connection to the bit line is realized or a MOS transistor having a higher threshold voltage is realized. The higher threshold voltage of the MOS transistor can be obtained by corresponding implantation in the channel region or by means of a higher gate oxide density.
Further semiconductor memories have been proposed which have diodes as memory cells. The diodes are each connected between word and bit lines (see, for example C. de Graaf et al., IEDM 1996, page 189). Due to the fact, however, that the diodes are disadvantageous in terms of electrical behavior compared with the transistors, these concepts have not gained acceptance in products.
Semiconductor-based memories allow random access to the stored information. The electrical power required to read the information is distinctly less than in a reading apparatus having a mechanical drive. Since a mechanical drive is not required for reading the information, the mechanical wear and the sensitivity to vibrations are obviated. These memories can therefore be used for mobile systems as well. However, owing to the MOS transistor required per memory cell, they are technologically complicated to fabricate.
It is accordingly an object of the invention to provide a memory cell configuration and a fabrication method, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows fabrication with a reduced technological complexity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a semiconductor layer structure having a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines running transversely to the word lines, and an insulating layer between the word lines and the bit lines;
the insulating layer being formed with contact holes at crossover points between the bit lines and the word lines;
resistors having a resistance higher than a resistance of the word lines and a resistance of the bit lines connected between the word lines and the bit lines, the resistors each being arranged in a respective the contact hole between a respective the bit line and a respective the word line; and
a sense amplifier connected to each the bit line for regulating a potential on the respective the bit line to a reference potential and for outputting an output signal.
The word lines may run both above and below the bit lines. Resistors having a higher resistance than the word lines and the bit lines are connected between the word lines and the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off.
In this memory cell configuration, the logic values zero and one are realized as follows: resistors having two different resistances for the two different logic values are realized, or as follows: a resistor is fabricated for one of the logic values and no resistor is fabricated for the other of the logic values. In the case where a resistor is fabricated only for one of the logic values, it is accordingly the case that, in accordance with the stored information, only a portion of the bit lines is connected to a portion of the word lines via a resistor.
In this memory cell configuration, word lines and bit lines are connected to one another. The memory cell configuration can nevertheless be read, since the bit lines can be regulated to a reference potential in each case by means of the sense amplifier. The bit lines are regulated to ground potential, for example. If a word line is selected by the application of a signal, while all the other word lines are connected to reference potential, for example ground potential, then the output signal of the sense amplifier is dependent on the resistor via which the word line is connected to the bit line. This resistor may have an infinite value for the case where one of the logic values is realized by no resistor being present.
In accordance with an added feature of the invention, the sense amplifier contains a feedback operational amplifier. If the inverting input of the operational amplifier is connected to the bit line, and the non-inverting input to ground potential, and if the output is connected to the inverting input via a feedback resistor, then the operational amplifier regulates the potential at the inverting input, that is to say on the bit line, to zero volts. The resistance of the resistor between the respective bit line and the selected word line then follows from the output signal of the operational amplifier and the feedback resistor of the operational amplifier.
In accordance with an additional feature of the invention, the resistors comprise first resistors and second resistors with mutually different resistances. The first resistors represent a first logic value and the second resistors represent a second logic value.
In accordance with another feature of the invention, the number of word lines is greater than the number of bit lines. This reduces the required number of sense amplifiers.
The memory cell configuration can be realized in different ways. By way of example, it can be realized using thin-film technology on a support plate made, for example, of glass, silicon or metal. The memory cell configuration is preferably realized as a semiconductor layer structure on a semiconductor substrate. A silicon wafer or an SOI substrate, for example, is suitable as the semiconductor substrate. The word lines and/or bit lines are formed as strip-type structures made of conductive material, for example metal, doped silicon and/or metal silicide, or as strip-type doped regions in the surface of the substrate. They are preferably fabricated at the same time as the formation of an interconnect plane, for example gate plane or metalization plane.
The use of a semiconductor substrate has the advantage that peripheral components, for example the sense amplifier, drive circuits or the like, can be contained in an integrated manner in the substrate.
Furthermore, the memory cell configuration can be realized in the two uppermost metalization layers of a semiconductor component which contains the sense amplifiers, inter alia, in the lower region.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating a memory cell configuration, which comprises the following steps:
forming a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, and an insulating layer on a surface of a substrate, whereby the word lines run transversely to the bit lines and the insulating layer is arranged between the word lines and the bit lines;
opening contact holes each arranged between one of the bit lines and one of the word lines at predetermined crossover points between the bit lines and the word lines in the insulating layer;
forming a resistor in each of the contact holes and connecting the resistor between the respective bit line and the respective word line, the resistor having a higher resistance than the bit lines and the word lines;
producing sense amplifiers each connected to a respective bit line, and enabling the sense amplifiers to regulate a potential on the respective bit line to a reference potential and to output an output signal.
In accordance with a further feature of the invention, the resistors are formed with at least one of the materials Al2O3, SiO2, polysilicon, or amorphous silicon.
In accordance with again a further feature of the invention, the word lines are formed as follows:
first of all, an auxiliary structure is produced with strip-type elements;
a conductive layer is formed with essentially conformal edge coverage; and
the word lines are then produced in the form of conductive spacers from the conductive layer by anisotropic etching which is selective with respect to the auxiliary structure.
In other words, the memory cell configuration is preferably fabricated using semiconductor technology. The word lines and bit lines are each formed by layer depositions and subsequent patterning or by doping with the aid of photolithographic process steps. The resistors are preferably produced by etching a contact hole at the crossover points between the relevant word lines and bit lines and forming a resistor in the contact hole. Since the memory cell configuration is programmed by this contact hole etching and formation of the resistor and it is generally regarded as advantageous to perform this programming at the end of production, it is advantageous to open the contact holes directly before the last metalization plane.
The contact holes can also be opened and suitably filled after the formation of bit lines and word lines.
With regard to the process of reading out the data, it is advantageous to realize the resistors with resistances in the megohm range. It lies within the scope of the invention to provide the resistors with an insulating tunnel layer. Tunnel layer is the term used to denote an insulating layer which is so thin that charge carriers can surmount the tunnel layer by virtue of the quantum mechanical tunneling effect and an electric current thus flows through the tunnel layer. Tunnel layers are usually formed from oxides, for example Al2O3 or SiO2. In this case, the resistor comprises the tunnel layer and a conductive layer, for example doped polysilicon constituting the connection to the associated word or bit line. As an alternative, the resistors may be formed from weakly doped polysilicon and/or amorphous silicon.
In order to increase the packing density, it is advantageous to form the word lines using a spacer technique. To that end, first of all an auxiliary structure having strip-type elements is produced. A conductive layer is subsequently formed with essentially conformal edge coverage. By means of anisotropic etching which is selective with respect to the auxiliary structure, the word lines are then formed in the form of conductive spacers from the conductive layer. The dimensions of the auxiliary structures are limited, by the photolithography used, to a width and a spacing of the strip-type elements of F in each case, that is to say a minimum structure size that can be fabricated using the respective lithography. The conductive spacers form on both sidewalls of the strip-type elements, with the result that the density of the word lines is increased by a factor of 2 in comparison with the density that can be obtained by lithography.
During the read-out of the memory cell configuration having i bit lines and j word lines, the resistance of a driven word line turns out to have a maximum value of Rmax/i from the parallel circuit of i resistors having a resistance of Rmax. If a resistor with a value of 1 Mxcexa9, for example, is produced for one of the logic values, and if the feedback resistor also has a value of 1 Mxcexa9, then a signal of 1 mV results for one logic value and a signal of 1 V results for the other logic value, given a total leakage current of 1 nA, provided that the word line is selected with a signal of 1 V, for example. The resistance of the driven word line is then at least 10 kxcexa9 given 100 bit lines, for example.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is. illustrated and described herein as embodied in a memory cell configuration and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.